Memory System Compression and Its Benefits

This paper presents an overall analysis of the redundancy in the information (addresses, instructions, and data) stored and exchanged between the processor and the memory system and evaluates the potential of compression in improving performance, power consumption, and cost of the memory system. Analysis of traces obtained with Sun Microsystems’ Shade simulator simulating SPARC executables of nine integer and six floating-point programs in the SPEC CPU2000 benchmark suite yield impressive results. Well-designed compression schemes may provide benefits in performance, power, and cost that far outweigh their overheads constituting extra time, logic, and power for compression and decompression. This will be more so in the future since the speed, size, and power consumption of logic (which will be used to perform compression/decompression) are improving and are projected to improve at a much higher rate compared to those of interconnect (which will be used to communicate the information), both on-chip and off-chip. Keywords— Address compression, bandwidth, cache, costeffective design, data compression, entropy, instruction compression, latency, lossless compression, low power, Markov models, memory, register file, storage, traffic.